The invention relates to memory devices comprising a memory array having a plurality of non-volatile memory cells, like NROM memory devices (nitride read only memory) or devices comprising floating gate transistor cells, for instance. The invention in particular refers, for instance, to flash memory devices comprising sectors of non-volatile memory cells, all memory cells of a particular sector being erased commonly if an erasing operation is performed in the respective sector of the memory array. The invention further refers to memory devices comprising memory cells that each are capable of storing at least one first bit at a first bit position and at least one second bit at a second bit position different from the first bit position, like twin-flash memory cells and multi-level cells.
In an actual memory device, predefined electrical potentials are provided in order to erase, to program or to read out memory cells. Conventionally the magnitude of these potentials is uniform for all memory cells of the memory device to which these respective potentials are applied. For instance, for programming any one of the memory cells, a predefined programming voltage is applied to an electrode of the respective memory cell to be programmed. The programming voltage is applied to the memory cell via a conductive line like a bitline, for instance. Further lines like wordlines, for instance, may be used for biasing further electrodes of the memory cells. However, in any case at least one predefined potential (like the programming voltage) is to be supplied in order to change the information stored in the memory cell.
The minimum voltage at which the information is actually changed in a memory cell is hereinbelow referred to as the threshold voltage. If a programming voltage having a magnitude larger than the threshold voltage of the memory cell is applied, the memory cell is programmed.
In an actual memory device the threshold voltage of a particular memory cell depends on the dimensions of microelectronic substructures of the respective memory cell. The threshold voltage mainly depends on the gate length. Furthermore, spatial dimensions like the gate oxide thickness, like dopant concentration profiles of source/drain regions and of LDD regions (lightly doped drain) as well as parasitic effects resulting from microelectronic structures arranged close to the memory cell all may influence the exact magnitude of the threshold voltage of the individual cell. Accordingly, in an actual memory device each memory cell has a slightly different threshold voltage.
In particular in case of flash memory devices, apart from tolerances in the exact dimensions of the structural elements of the memory cell (due to lithographic parameters and misalignments), the voltage-drain-source effect, for instance, influences the threshold voltage. The voltage-drain-source effect entails different degrees of programming efficiency that depending on whether, in a transistor cell structure having two bit positions for storing one respective bit (or multi-bit due to multilevel cells), the other bit is programmed or not. Furthermore, other intrinsic and systematic design related effects also may influence the threshold voltage.
Furthermore, in case of a flash memory having NROM twin flash memory cells, pairs of memory cells are provided, each pair being formed of a transistor structure based on MOSFET technology and including a charge-trapping layer like a silicon nitride layer capable of storing two digital information above a respective first and/or second source/drain region. Depending on whether the programming voltage is supplied to a conductive line contacting the first source/drain region of the memory cell or to the other conductive line contacting the second source/drain region of the memory cell, either a first bit (close to the first source/drain region) or a second bit (close to the second source/drain region) is programmed. Since the total amount of electrical charges stored in the charge-trapping layer is the sum of the electrical charges constituting the first and the second bit, the threshold voltage for programming one of these bits depends on the programming status (programmed or erased) of the respective other bit. Due to this program-neighbor-effect, in the respective other cell of the cell pair leakage currents to a further conductive line (for instance to an adjacent conductive line) influence the threshold voltage for programming the other bit in the cell pair.
The threshold voltage of an individual memory cell is further influenced by differences of the layout and the design of the memory cells and their contacts to conductive lines. In general any arrangement of conductive elements in close distance from the memory cell influences the magnitude of a threshold voltage.
Accordingly, there are several influences on the threshold voltage of the particular memory cell, at least some of these influences being systematic due to the overall design of the memory array.
Usually a memory array comprises a plurality of equally-sized subsections (memory areas) arranged at distances from one another, which distances are larger than the distances between two memory cells within the same subsection. Due to the limited access time for programming the memory cells and to the limited conductivity of thin conductor lines accessing the memory cells, segmented conductive lines (segmented wordlines or bitlines) are usually provided. Furthermore, sense amplifiers arranged in plural columns or rows further subdivide the memory array, for instance. Accordingly, any memory array comprises equally-sized memory areas that have the same corresponding internal design and layout. Since all memory areas are equally sized, each memory area comprises the same number of memory cells and the same number of conductive lines connecting the memory cells. Even when considering that the internal design of many of these memory areas is mirror-inverted with view to the internal design of further memory areas, all these memory areas are corresponding to one another.
In case of flash memories comprising sectors of commonly erasable memory cells, the memory areas are subsections of the sectors, for instance. Within a memory area, the threshold voltage of the memory cells is at least partially influenced systematically by the position, within the memory area, of the conductive line (for providing the programming voltage) to which the memory cell is connected.